library ieee;
use ieee.std_logic_1164.all;

entity signext_tb is
end signext_tb;

architecture behav of signext_tb is
    component signext
        port(
        a: in std_logic_vector(15 downto 0);
        y: out std_logic_vector(31 downto 0)
        );
    end component;
begin
    -- HACER!!!
end behav;
